A Heuristic for Clock Selection in High-Level Synthesis

Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or exact (and expensive) methods have been used for clock selection. This paper presents a novel heuristic approach for near-optimal clock selection for synthesis systems. This technique is based on critical paths in the dataflow graph. In addition, we introduce and exploit a new figure of merit called the activity factor to choose the best possible clock. Extensive experimental results show that the proposed technique is very fast and produces optimal solutions in a large number of cases; in those cases, where it is not optimal, we are off by just a few percent from optimal.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir
• Keywords: Computer Architecture, Near-optimal Clock Selection, Optimal Solutions, Synthesis Systems, VLSID 2002