Transistor Flaring in Deep Submicron-Design Considerations

Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes the channel length to vary along the transistor width. It seriously impacts self-alignment of the CMOS process, causes transistor-matching issues, and makes accurate transistor modeling difficult. It can have significant adverse yield impact. In this paper, the effect, its consequences, and different solutions are examined. A methodology for modeling the effect of flaring on transistor performance is introduced. Different solutions for high density and high performance designs are proposed.

• Type: Conference
• Year: 2002
• Where: VLSID
• Authors: Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh
• Keywords: Accurate Transistor Modeling, Computer Architecture, Transistor Performance, Transistor Width, VLSID 2002