Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling

Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate architecture, the Fully-Buffered DIMM. This new standard replaces the conventional memory bus with a narrow, high-speed interface between the memory controller and the DIMMs. This paper examines how traditional DDRx based memory controller policies for scheduling and row buffer management perform on a FullyBuffered DIMM memory architecture. The split-bus architecture used by FBDIMM systems results in an average improvement of 7% in latency and 10% in bandwidth at higher utilizations. On the other hand, at lower utilizations, the increased cost of serialization resulted in a degradation in latency and bandwidth of 25% and 10% respectively. The split-bus architecture also makes the system performance sensitive to the ratio of read and write traffic in the workload. In larger configurations, we found t...

• Type: Conference
• Year: 2007
• Where: HPCA
• Authors: Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob
• Keywords: Computer Architecture, DIMM Memory Architecture, HPCA 2007, Memory Bus Widths, Memory Controller Policies