Power-Aware Control Speculation through Selective Throttling

With the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors increase their clock frequency by lengthening the pipeline, which puts more pressure on the branch prediction engine since branches take longer to be resolved. Branch mispredictions are responsible for around 28% of the power dissipated by a typical processor due to the useless activities performed by instructions that are squashed. This work focuses on reducing the power dissipated by mis-speculated instructions. We propose Selective Throttling as an effective way of triggering different power-aware techniques (fetch throttling, decode throttling or disabling the selection logic). The particular set of techniques applied to each branch is dynamically chosen depending on the branch prediction confidence level. For branches with a low confidence on the prediction, the ...

• Type: Conference
• Year: 2003
• Where: HPCA
• Authors: Juan L. Aragón, José González, Antonio González
• Keywords: Aggressive Throttling Mechanism, Branch Prediction Confidence, Computer Architecture, Confidence Branch Predictions, HPCA 2003