TCP: Tag Correlating Prefetchers

Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recently, sophisticated hardware correlating prefetching mechanisms have been proposed, in some cases coupled with some form of dead-block prediction. In many proposals, however, correlating prefetchers demand a significant investment in hardware. In this paper we show that correlating prefetchers that work with tags instead of cache-line addresses are significantly more resource-efficient, providing equal or better performance than previous proposals. We support this claim by showing that per-set tag sequences exhibit highly repetitive patterns both within a set and across different sets. Because a single tag sequence can capture multiple address sequences spread over different cache sets, significant space savings can be achieved. We propose a tag-based prefetcher called a Tag Correlating Prefetcher (TCP). Even wi...

• Type: Conference
• Year: 2003
• Where: HPCA
• Authors: Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
• Keywords: Address-based Correlating Prefetchers, Computer Architecture, Correlating Memory Prefetchers, HPCA 2003, Tag Correlating Prefetcher