A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns

As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interconnects like buses, point-to-point wires and regular topologies may suffer from poor resource sharing in the time and space domains, leading to high contention or low resource utilization. In this paper, we propose a design methodology for constructing networks for special-purpose computer systems with well-behaved (known) communication characterictics. A temporal and spatial model is proposed to define the sufficient condition for contention-free communication. Based upon this model, a design methodology using a recursive bisection technique is applied to systematically partition a parallel system such that the required number of links and switches is minimized while achieving low contention. Results show that the design methodology can generate more optimized on-chip networks with up to 60% fewer resources ...

• Type: Conference
• Year: 2003
• Where: HPCA
• Authors: Wai Hong Ho, Timothy Mark Pinkston
• Keywords: Computer Architecture, Design Methodology, HPCA 2003, Optimized On-chip Networks, Recursive Bisection Technique