Reevaluating Online Superpage Promotion with Hardware Support

fipical translation lookaside buffers (TLBs)can map a far smaller region of memory than application footprints demand, and the cost of handling TLB misses therefore limits the performance of an increasing number of applications. This bottleneck can be mitigated by the use of superpages, multiple adjacent virtual memory pages that can be mapped with a single TLB entry, that extend TLB reach without significantly increasing size or cost. We analyze hardware/sofrware tradeoffsfor dynamically creating superpages. This study extends previous work by using execution-driven simulation to compare creating superpages via copying with remapping pages within the nienioiy controller, and by exaniining how the tradeoffs change when moving from a single-issue to a superscalar processor model. Wefind that remapping-based promotion outperforms copyingbased promotion. ofren signifcantly. Copying-based promotion is slightly more effective on superscalar processors than on single-issue processors, and t...

• Type: Conference
• Year: 2001
• Where: HPCA
• Authors: Zhen Fang, Lixin Zhang, John B. Carter, Wilson C. Hsieh, Sally A. McKee
• Keywords: Computer Architecture, HPCA 2001, Single Tlb Entry, TLB Misses, TLB Reach