A System-level Network-on-Chip Simulation Framework Integrated with Low-level Analytical Models

—This paper presents a system-level Network-on-Chip modeling framework that integrates transaction-level model and analytical wire model for design space exploration. It enables the analysis of influence of physical wire properties on the system performance and power dissipation in early design stages. SystemC provides the infrastructure to integrate transaction-level model and low-level models. By utilizing approximate timing, different temporal granularity can be used, leading to fast simulation speed. Six deep-submicron CMOS processes from 180nm to 45nm are used to evaluate the performance/power of NoC. Additionally, temporal and spatial NoC power analysis under different traffic conditions provides an effective basis for power/thermal optimization and design space exploration in early design stages.

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Jinwen Xi, Peixin Zhong
• Keywords: Design Space Exploration, Early Design Stages, Hardware, ICCD 2006, Spatial Noc Power