Trends and Future Directions in Nano Structure Based Computing and Fabrication

— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overcome in the near future, nanoscale devices will have high manufacturing defect rates and will operate at reduced noise margins, exposing computation to higher soft error rates. Thus, a key challenge for the future will be building fault and defecttolerant computing systems. Researchers are looking to develop hybrid systems that combine on the same chip CMOS-based circuitry with any number of alternatives, including circuits composed of nanowire or carbon nanotube devices. The big advantage of including these new devices on the same chip is the increased device densities, and potential drop in fabrication costs. On the other hand, integrating very large numbers of devices on a single chip leads to questions of how to manage so many devices with tight constraints on cost, performance, power, and reliability, with...

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: R. Iris Bahar
• Keywords: Carbon Nanotube Devices, Hardware, ICCD 2006, Nanoscale Devices, Silicon Cmos Devices