Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug

Abstract— This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator.

• Type: Conference
• Year: 2006
• Where: ICCD
• Authors: Marc Boule, Jean-Samuel Chenard, Zeljko Zilic
• Keywords: Assertion Completion, Hardware, Hardware Assertion Checkers, ICCD 2006, Paper Presents Techniques