On-Chip Transparent Wire Pipelining

Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects.

• Type: Conference
• Year: 2004
• Where: ICCD
• Authors: Mario R. Casu, Luca Macchiarulo
• Keywords: Gate Delays, Hardware, ICCD 2004, System-level Wire Pipelining, Wire Delays