Sciweavers

DATE
2005
IEEE
99views Hardware» more  DATE 2005»
14 years 5 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
ICCD
2004
IEEE
71views Hardware» more  ICCD 2004»
14 years 8 months ago
On-Chip Transparent Wire Pipelining
Wire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from bein...
Mario R. Casu, Luca Macchiarulo