High-level synthesis of distributed logic-memory architectures

Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resources (computing logic, memories, interconnect, etc.) throughout a chip, while restricting computations and communications to geographic proximities. In this paper, we present a methodology for high-level synthesis (HLS) of distributed logic-memory architectures, i.e., architectures that have logic and memory distributed across several partitions in a chip. Conventional HLS tools are capable of extracting parallelism from a behavior for architectures that assume a monolithic controller/datapath communicating with a memory or memory hierarchy. This work provides techniques to extend the synthesis frontier to more general architectures that can extract both coarse- and fine-grained parallelism from data accesses and computations in a synergistic manner. Our methodology selects many possible ways of organizing dat...

• Type: Conference
• Year: 2002
• Where: ICCAD
• Authors: Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
• Keywords: Applications Require Architectures, Conventional Hls Techniques, Conventional HLS Tools, Hardware, ICCAD 2002