Test-model based hierarchical DFT synthesis

With increasing design sizes and adoption of System on a Chip (SoC) methodology, design synthesis and test automation tools are hitting capacity and performance bottlenecks. Currently, hierarchical synthesis flows for large designs lack complete designfor-test (DFT) support. With this paper, we address a solution,

• Type: Conference
• Year: 2002
• Where: ICCAD
• Authors: Sanjay Ramnath, Frederic Neuveux, Mokhtar Hirech, Felix Ng
• Keywords: Design Synthesis, Hardware, Hierarchical Synthesis, ICCAD 2002, Test Automation Tools