Binning optimization based on SSTA for transparently-latched circuits

With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transparent latches are widely used. In this paper, we formulate and solve the binning optimization problem that decides the bin boundaries and their testing order to maximize the benefit (considering the test cost) for a transparentlylatched circuit. The problem is decomposed into three sub-problems which are solved sequentially. First, to compute the clock period distribution of the transparently-latched circuit, a sample-based SSTA approach is developed which is based on the generalized stochastic collocation method (gSCM) with Sparse Grid technique. The minimal clock period on each sample point is found by solving a minimal cycle ratio problem in the constraint graph. Second, a greedy algorithm is proposed to maximize the sales profit by iteratively assigning each boundary to its optimal position. Then, an optim...

• Type: Journal
• Year: 2009
• Where: ICCAD
• Authors: Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
• Keywords: Bin Boundaries, Clock Period, Hardware, ICCAD 2009, Testing Order