Cancellation of loads that return zero using zero-value caches

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads—loads accessing memory locations that contain the value “zero”—to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of all dynamic loads. We show that significantly many zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique—the Zero-Value Cache (ZVC)—to capitalize on zero loads, and we explore critical design options of such caches. We show that with a modest hardware investment (typically, a 512byte structure), we obtain speedups of up to 32%. Most importantly, ZVCs never reduce performance. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles – cache memories. General Terms Design, Performance, Experimentation. Keywords Cache, Zero Load, Load Criticality, Frequent Value...

• Type: Conference
• Year: 2009
• Where: ICS
• Authors: Md. Mafijul Islam, Sally A. McKee, Per Stenström
• Keywords: Dynamic Loads, ICS 2009, Loads—loads Accessing Memory, Theoretical Computer Science, Zero”—to Improve Performance