An ILP formulation for task mapping and scheduling on multi-core architectures

Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory architecture, and task mapping and scheduling. This paper presents an integer linear programming formulation for the task mapping and scheduling problem. The technique incorporates profiling-driven loop level task partitioning, task transformations, functional pipelining, and memory architecture aware data mapping to reduce system execution time. Experiments are conducted to evaluate the technique by implementing a series of DSP applications on several multi-core architectures based on dynamically reconfigurable processor cores. The results demonstrate that the proposed technique is able to generate high-quality mappings of realistic applications on the target

• Type: Conference
• Year: 2009
• Where: DATE
• Authors: Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan
• Keywords: DATE 2009, Hardware, Memory Architecture, Multi-core Architectures, Task Mapping