Buffer design and optimization for lut-based structured ASIC design styles

The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split off a long wire into several buffered wire segments for circuit performance improvement. In this paper, we are motivated to investigate the buffer insertion issues in LUT-based structured ASIC design style. We design the layouts of two dedicated buffers and extract the technology dependent parameters for evaluations. After that, we propose a channel migration technique, which employs both intra-channel migration and inter-channel migration, to alleviate the sub-channel saturation problem. The experimental results demonstrate that dedicated buffers are essential for structured ASIC design style. Categories and Subject Descriptors: B.7.1 [Integrated Circuits]: VLSI General Terms: Performance

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Po-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu
• Keywords: ASIC Design Style, Design Style, GLVLSI 2009, Structured Asic Design, VLSI