PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches

Many multi-core processors employ a large last-level cache (LLC) shared among the multiple cores. Past research has demonstrated that sharing-oblivious cache management policies (e.g., LRU) can lead to poor performance and fairness when the multiple cores compete for the limited LLC capacity. Different memory access patterns can cause cache contention in different ways, and various techniques have been proposed to target some of these behaviors. In this work, we propose a new cache management approach that combines dynamic insertion and promotion policies to provide the benefits of cache partitioning, adaptive insertion, and capacity stealing all with a single mechanism. By handling multiple types of memory behaviors, our proposed technique outperforms techniques that target only either capacity partitioning or adaptive insertion. Categories and Subject Descriptors

• Type: Conference
• Year: 2009
• Where: ISCA
• Authors: Yuejian Xie, Gabriel H. Loh
• Keywords: Cache, Cache Management, Hardware, ISCA 2009, Multiple Cores