Architectural core salvaging in a multi-core processor for hard-error tolerance

The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a priori, either at manufacture-time or in the field, cores with such errors must be disabled in the absence of hard-error tolerance. While caches, with their regular and repetitive structures, are easily covered against hard errors by providing spare arrays or spare lines, structures within a core are neither as regular nor as repetitive. Previous work has proposed microarchitectural core salvaging to exploit structural redundancy within a core and maintain functionality in the presence of hard errors. Unfortunately microarchitectural salvaging introduces complexity and may provide only limited coverage of core area against hard errors due to a lack of natural redundancy in the core. This paper makes a case for architectural core salvaging. We observe that even if some individual cores cannot execute certain opera...

• Type: Conference
• Year: 2009
• Where: ISCA
• Authors: Michael D. Powell, Arijit Biswas, Shantanu Gupta, Shubhendu S. Mukherjee
• Keywords: Architectural Core Salvaging, Core Salvaging, Hard Errors, Hardware, ISCA 2009