Variation-aware resource sharing and binding in behavioral synthesis

— As technology scales, the delay uncertainty caused by process variations has become increasingly pronounced in deep submicron designs. In the presence of process variations, worst-case timing analysis may lead to overly conservative synthesis, and may end up using excess resources to guarantee design constraints. In this paper, we propose an efficient variation-aware resource sharing and binding algorithm in behavioral synthesis, which takes into account the performance variations for functional units. The performance yield, which is defined as the probability that the synthesized hardware meets the target performance constraints, is used to evaluate the synthesis result. An efficient metric called statistical performance improvement, is used to guide resource sharing and binding. The proposed algorithm is evaluated within a commercial synthesis framework that generates optimized RTL netlists from behavioral specifications. The effectiveness of the proposed algorithm is demonst...

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Feng Wang 0004, Yuan Xie, Andres Takach
• Keywords: ASPDAC 2009, Hardware, Process Variations, Resource Sharing, Worst-case Timing Analysis