Structural Synthesis of Four-Quadrant Multiplier Based on Hierarchical Topology

This paper presents a method towards automatic structural synthesis of analog multiplier based on a hierarchilogy “super-topology”, which is abstracted from the most standard four-quadrant multipliers. The essential components in the super-topology are four identical cells, which consist of several MOS-transistors and determine features and performances of multipliers. We build all possible cells within 3 transistors. Experimental results present three new multiplier structures with simulation results to show the creativity of our method.

• Type: Conference
• Year: 2008
• Where: DATE
• Authors: Xiaoying Wang, Lars Hedrich
• Keywords: Analog Multiplier, Automatic Structural Synthesis, DATE 2008, Hardware, Standard Four-quadrant Multipliers