Scheduling algorithms for unpredictably heterogeneous CMP architectures

In future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ among the cores in an unanticipated manner. Under this scenario, naïve assignments of applications to cores degraded by various faults and variations may result in large performance losses and power inefficiencies. We propose scheduling algorithms based on the Hungarian Algorithm and artificial intelligence (AI) search techniques that account for this future uncertainty in core characteristics. These thread assignment policies effectively match the capabilities of each degraded core with the requirements of the applications, achieving an ED2 only 3.2% and 3.7% higher, respectively, than a baseline eight core chip multiprocessor with no degradation, compared to over 22% for a round robin policy.

• Type: Conference
• Year: 2008
• Where: DSN
• Authors: Jonathan A. Winter, David H. Albonesi
• Keywords: Computer Networks, Core Chip Multiprocessor, DSN 2008, Large Performance Losses, Large-scale Multi-core Microprocessors