VEAL: Virtualized Execution Accelerator for Loops

Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunction with general purpose processors to achieve future performance goals. There is a serious drawback to accelerators, though: binary compatibility. An application compiled to utilize an accelerator cannot run on a processor without that accelerator, and applications that do not utilize an accelerator will never use it. To overcome this problem, we propose decoupling the instruction set architecture from the underlying accelerators. Computation to be accelerated is expressed using a processor’s baseline instruction set, and light-weight dynamic translation maps the representation to whatever accelerators are available in the system. In this paper, we describe the changes to a compilation framework and processor system needed to support this abstraction for an important set of accelerator designs that suppor...

• Type: Conference
• Year: 2008
• Where: ISCA
• Authors: Nathan Clark, Amir Hormati, Scott A. Mahlke
• Keywords: Domain Specific Accelerators, Effective Loop Accelerators, Hardware, Instruction Set, ISCA 2008