Reduced Delay BCD Adder

Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 times slower than binary arithmetic implemented in hardware. Therefore, hardware support for decimal arithmetic is required. In this paper, a reduced delay binary coded decimal (BCD) adder is proposed. The proposed adder improves the delay of BCD addition by increasing parallelism. On the critical-path of the proposed BCD adder, there are two 4-bit binary adders, a carry network, one AND gate, and one OR gate. To make area and delay comparison, the proposed adder and previously proposed five decimal adders are implemented in VHDL and synthesized using 0.18 micron TSMC ASIC library. Synthesis results obtained for 64-bit addition (16 decimal digits) show

• Type: Conference
• Year: 2007
• Where: ASAP
• Authors: A. A. Bayrakci, A. Akkas
• Keywords: ASAP 2007, Binary Coded Decimal, Decimal Arithmetic, Decimal Data, Distributed And Parallel Computing