Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow

In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable compilation flow. The toolchain is used to develop an initial processor design, asses the performance and identify the potential bottlenecks. A second design iteration results in a fully optimized ASIP with a VLIW instruction set which allows for high degree of parallelism among the functional units inside the ASIP and has dedicated instructions to accelerate typical packet processing tasks. This way, a single processor is capable of handling the complete throughput of a gigabit Ethernet link. To reach the target of a 10 Gbit/s Ethernet access node several processors operate in parallel in a multicore environment.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: K. Van Renterghem, P. Demuytere, Dieter Verhulst, Jan Vandewege, Xing-Zhi Qiu
• Keywords: DATE 2007, Ethernet Access Node, Hardware, Instruction Set, Instruction Set Processor