Simulation-based reusable posynomial models for MOS transistor parameters

We present an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the Geometric Programming flow for automatic circuit sizing. The models are reusable for multiple circuits on a given Silicon technology and hence don’t adversely affect the scalability of the Geometric Programming approach. The proposed method is a combination of genetic algorithms and Quadratic Programming. It is the only approach for posynomial modeling with real-valued exponents which is easily extensible to different error metrics. We compare the proposed technique with state-of-art posynomial/monomial modeling techniques and show its superiority.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Varun Aggarwal, Una-May O'Reilly
• Keywords: DATE 2007, Geometric Programming, Geometric Programming Approach, Hardware, State-of-art Posynomial/monomial Modeling