Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry

RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due to high frequencies involved, testing these chips is both complicated and expensive. While the areas of Automated testing and Self-test have received significant attention over the past few years, no formal framework of fault-models or sensitivity-models exists in the RF domain. This paper describes a Sensitivity Analysis methodology as a first step towards such a framework. It is applied towards a Low Noise Amplifier, and a case-study application is discussed by using design and experimental results of an adaptive LNA designed in the IBM6RF 0.25 µm CMOS process.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: Tejasvi Das, P. R. Mukund
• Keywords: DATE 2007, Hardware, Modern Ic Systems, Sensitivity Analysis Methodology, µm Cmos Process