A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta Modulator

− This paper reports the transistor-level design of a 130-nm CMOS continuous-time cascade ΣΔ modulator. The modulator topology, directly synthesized in the continuous-time domain, consists of a third-order stage followed by a second-order stage, both realized using Gm-C integrators and a 4-bit internal quantizer. Dynamic element matching is included to compensate for the non-linearity of the feedback digital-to-analog converters. The estimated power consump

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Ramon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández
• Keywords: 4-bit Internal Quantizer, CMOS Continuous-time Cascade, Continuous-time Domain, ISCAS 2007