Characterization of a Fault-tolerant NoC Router

— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore architectures. Another concern for these architectures is increasing global wire lengths with associated issues leading to network-on-chips (NoC) becoming standard for on-chip global communication. We recognize these issues and present an onchip generic fault-tolerant routing algorithm. The microarchitecture of a NoC router implementing the proposed routing algorithm for a k-ary 2-cube topology is provided. The proposed router works in two phases. In the first phase, the network is explored for an existing path between sourcedestination pairs after reset or during system reconfiguration after fault detection. Existing paths are cached and used in the second phase of data communication during normal system operation. The presented router architecture also proposes a concept of dynamic multiplexing of virtual c...

• Type: Conference
• Year: 2007
• Where: ISCAS
• Authors: Sumit D. Mediratta, Jeffrey T. Draper
• Keywords: ISCAS 2007, NoC Fault-tolerant Router, Router, Routing Algorithm