GlitchLess: an active glitch minimization technique for FPGAs

This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable delay elements within the logic blocks of an FPGA to programmably align the arrival times of early-arriving signals to the inputs of the lookup tables and to filter out glitches generated by earlier circuitry. On average, the proposed technique eliminates 91% of the glitching, which reduces overall FPGA power by 18%. The added circuitry increases overall area by 5% and critical-path delay by less than 1%. Furthermore, since it is applied after routing, the proposed technique requires no modifications to the existing FPGA routing architecture or CAD flow. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Gate Arrays General Terms Design. Keywords Field-Programmable Gate Arrays, Power Minimization.

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton
• Keywords: FPGA, FPGA 2007, FPGA Routing Architecture, Hardware, Overall Fpga Power