Data Reuse Driven Memory and Network-On-Chip Co-Synthesis

NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a significant source of energy consumption and many attempts at energy efficient NoC synthesis have been proposed. However, in addition to the communication subsystem, the memory subsystem is an important contributor to chip energy consumption. These two subsystems are not independent, and a design with the lowest memory power consumption may not have the lowest overall power consumption. In this paper we propose to exploit a data reuse analysis approach for cosynthesis of memory and NoC communication architectures. We present a co-synthesis heuristic targeting NoCs, such as Æthereal, with mesh topology. We show that our data reuse analysis based synthesis reduces communication energy alone by 31% on average as well as memory and communication energy by 44% on average in comparison with the similar approaches that do ...

• Type: Conference
• Year: 2007
• Where: IESS
• Authors: Ilya Issenin, Nikil Dutt
• Keywords: Communication, Data Reuse Analysis, Embedded Systems, IESS 2007, Memory Subsystem