Sciweavers

DAC
2001
ACM
16 years 7 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
DAC
2001
ACM
16 years 7 months ago
Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk
Yehia Massoud, Jamil Kawa, Don MacMillen, Jacob Wh...
DAC
2001
ACM
16 years 7 months ago
Watermarking of SAT using Combinatorial Isolation Lemmas
Watermarking of hardware and software designs is an effective mechanism for intellectual property protection (IPP). Two important criteria for watermarking schemes are credibility...
Rupak Majumdar, Jennifer L. Wong
154
Voted
DAC
2001
ACM
16 years 7 months ago
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems
Power-aware systems are those that must make the best use of available power. They subsume traditional low-power systems in that they must not only minimize power when the budget ...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi ...
DAC
2001
ACM
16 years 7 months ago
Fast Statistical Timing Analysis By Probabilistic Event Propagation
Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Ang...
DAC
2001
ACM
16 years 7 months ago
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level syste...
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed...
DAC
2001
ACM
16 years 7 months ago
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems
This paper addresses battery-aware static scheduling in batterypowered distributed real-time embedded systems. As suggested by previous work, reducing the discharge current level ...
Jiong Luo, Niraj K. Jha
DAC
2001
ACM
16 years 7 months ago
High-Quality Operation Binding for Clustered VLIW Datapaths
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with large number of register file ports. E...
Viktor S. Lapinskii, Margarida F. Jacome, Gustavo ...
DAC
2001
ACM
16 years 7 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...