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IEICET
2007
2007
A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation
Real-time Traffic| Added | 14 Dec 2010 |
| Updated | 14 Dec 2010 |
| Type | Journal |
| Year | 2007 |
| Where | IEICET |
| Authors | Ching-Yuan Yang, Jung-Mao Lin |
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