Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems

This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ring oscillator and a linear phase detector whereas the second implementation uses a multiphase LC oscillator and a bang-bang phase/frequency detector. Fabricated in 0.18m CMOS technology, the power consumption of each of the circuits is less than 100 mW. The rms jitter of the output clock for the two prototypes is 1 ps and 0.8 ps, respectively, while the latter achieves a capture range of more than 14%.

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Jafar Savoj, Behzad Razavi
• Keywords: DAC 2001, Data Recovery Circuits, Design Automation, Linear Phase Detector, Multiphase Lc Oscillator