A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection

We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (QoB)" for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells for one-bit information (i.e. 14T/bit). Monte Carlo simulation demonstrates that, in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.20V and 0.26V, respectively, with a bit error rate of 10-8 kept. The cell area overhead is 11%, compared to the conventional 6T cell in the normal mode.

• Type: Conference
• Year: 2009
• Where: VLSID
• Authors: Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
• Keywords: Bit Error Rate, Computer Aided Design, Dependable Mode, Normal Mode, VLSID 2009