Abstract— This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topo...
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (Q...
Increasing the number of cores in a multi-core processor reduces per-core performance. On the other hand, providing more resources to each core limits the number of cores on a chi...
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time ...
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...