Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs

This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization schemes commonly found in highlevel synthesis tools. Performing register optimization as part of synthesis process implies that the mapping between the specification variables and RTL registers is not bijective. We propose a formalization of dynamic variable-register mapping, and techniques based on symbolic analysis and higher-order logic theorem proving for verifying synthesized RTL designs. The proposed verification methodology has been successfully implemented using the PVS theorem prover.

• Type: Conference
• Year: 1999
• Where: DATE
• Authors: Nazanin Mansouri, Ranga Vemuri
• Keywords: DATE 1999, Hardware, PVS Theorem Prover, Rtl Designs, RTL Registers