DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Estimating peak power involves optimization of the circuit's switching function. We propose genetic spot expansion and optimization in this paper to estimate tight peak power...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
There is an increasing research interest in system level design languages which can carry designers from specification to implementation of system-on-a-chip. Unfortunately, two of...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more e ci...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
This paper addresses the problem of efficient functional simulation of synchronous digital systems. A technique based on the use of Decision Diagrams (DD) for representing the fun...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Methods for performing component matching by expressing an arithmetic specification and a bit-level description of an implementation as word-level polynomials have been demonstrat...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
In this paper, a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and a...
DATE
1999
IEEE
14 years 3 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...