Adapting cache line size to application behavior

A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. Optimalsize mayalso change during application execution. This paper describes a cache in which the line (fetch) size is continuously adjusted by hardware based on observed application accesses to the line. The approach can improve the miss rate, even over the optimal for the xed line size, as well as signi cantly reduce the memory tra c.

• Type: Conference
• Year: 1999
• Where: ICS
• Authors: Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau, Xiaomei Ji
• Keywords: Cache Line Size, Distributed And Parallel Computing, ICS 1999, Line Size, Xed Line Size