Sciweavers

DM
2010
86views more  DM 2010»
13 years 9 months ago
On the simple connectedness of hyperplane complements in dual polar spaces, II
Suppose is a dual polar space of rank n and H is a hyperplane of . Cardinali, De Bruyn and Pasini have already shown that if n 4 and the line size is greater than or equal to fo...
Justin McInroy, Sergey Shpectorov
IMS
2000
125views Hardware» more  IMS 2000»
14 years 4 months ago
Compiler-Directed Cache Line Size Adaptivity
The performance of a computer system is highly dependent on the performance of the cache memory system. The traditional cache memory system has an organization with a line size tha...
Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbau...
ICS
1999
Tsinghua U.
14 years 4 months ago
Adapting cache line size to application behavior
A cache line size has a signi cant e ect on missrate and memorytra c. Today's computers use a xed line size, typically 32B, which may not be optimalfor a given application. O...
Alexander V. Veidenbaum, Weiyu Tang, Rajesh K. Gup...
ISVLSI
2003
IEEE
101views VLSI» more  ISVLSI 2003»
14 years 5 months ago
Energy Benefits of a Configurable Line Size Cache for Embedded Systems
Previous work has shown that cache line sizes impact performance differently for different desktop programs – some programs work better with small line sizes, others with larger...
Chuanjun Zhang, Frank Vahid, Walid A. Najjar