An algorithm for synthesis of system-level interface circuits

We describe an algorithm for the synthesis and optimization of interface circuits for embedded system components such as microprocessors, memory ASIC, and network subsystems with xed interfaces. The algorithm accepts the timing characteristics of two system components as input, and generates a combinational interface (glue logic) circuit. The algorithm consists of two parts. In the rst part, we determine the direct pin-topin connections in the interface circuit employing a 0/1 ILP formulation to minimize wiring area and dynamic power consumption. In the second part, we determine logic subcircuits in the interface circuit, utilizing the timing diagrams of the system components. The proposed algorithm has been implemented in a software package SYNTERFACE. Experimental results are presented to demonstrate the eectiveness of the algorithm.

• Type: Conference
• Year: 1996
• Where: ICCAD
• Authors: Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu
• Keywords: Algorithm, Combinational Interface, Hardware, ICCAD 1996, Interface Circuit