Analysis of power-clocked CMOS with application to the design of energy-recovery circuits

⎯ This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe properties of clocked signals. Next two types of power-clocked CMOS circuit constructions are introduced and analyzed in detail. Since the adiabatic switching requires slow-ramping of the power-clock, a clocked transmission gate and a four-stage clocked NP-domino circuit are presented, which receive trapezoidal and sinusoidal power-clocks, respectively. PSPICE simulations demonstrate the correct operation and energy-saving advantage of the proposed circuits.

• Type: Conference
• Year: 2000
• Where: ASPDAC
• Authors: Massoud Pedram, Xunwei Wu
• Keywords: ASPDAC 2000, Clocked, Clocked Signals, Hardware, Power-clocked Cmos