Analysis of power consumption on switch fabrics in network routers

In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, internal buffers and interconnect wires inside switch fabric architectures. A simulation platform is also implemented to trace the dynamic power consumption with bit-level accuracy. Using this framework, four switch fabric architectures are analyzed under different traffic throughput and different numbers of ingress/egress ports. This framework and analysis can be applied to the architectural exploration for low power high performance network router designs. Categories and Subject Descriptors C.4 [Performance of Systems]: Design studies, Modeling techniques General Terms Design, Experimentation, Performance Keywords Networks on Chip, Interconnect Networks, Systems on Chip, Power Consumption

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Terry Tao Ye, Giovanni De Micheli, Luca Benini
• Keywords: DAC 2002, Design Automation, Dynamic Power Consumption, Power Consumption, Switch Fabric Architectures