An approach for implementing efficient superscalar CISC processors

An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targeted, the overall approach is applicable to other CISC ISAs. To provide high performance on frequently executed code sequences, fully transparent dynamic translation software decomposes CISC superblocks into RISC-style micro-ops. Then, pairs of dependent micro-ops are reordered and fused into macro-ops held in a large, concealed code cache. The macro-ops are fetched from the code cache and processed throughout the pipeline as single units. Consequently, instruction level communication and management are reduced, and processor resources such as the issue buffer and register file ports are better utilized. Moreover, fused instructions lead naturally to pipelined instruction scheduling (issue) logic, and collapsed 3-1 ALUs can be used, resulting in much simplified result forwarding logic. Steady state performance i...

• Type: Conference
• Year: 2006
• Where: HPCA
• Authors: Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith
• Keywords: Co-designed Cisc Processor, Computer Architecture, Four-wide Superscalar Processor, HPCA 2006, Two-wide Superscalar Processor