Sciweavers

HPCA
2011
IEEE
13 years 2 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
HPCA
2011
IEEE
13 years 2 months ago
Bloom Filter Guided Transaction Scheduling
Contention management is an important design component to a transactional memory system. Without effective contention management to ensure forward progress, a transactional memory...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
HPCA
2011
IEEE
13 years 2 months ago
Beyond block I/O: Rethinking traditional storage primitives
Over the last twenty years the interfaces for accessing persistent storage within a computer system have remained essentially unchanged. Simply put, seek, read and write have de...
Xiangyong Ouyang, David W. Nellans, Robert Wipfel,...
HPCA
2011
IEEE
13 years 2 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
HPCA
2011
IEEE
13 years 2 months ago
Calvin: Deterministic or not? Free will to choose
Most shared memory systems maximize performance by unpredictably resolving memory races. Unpredictable memory races can lead to nondeterminism in parallel programs, which can suff...
Derek Hower, Polina Dudnik, Mark D. Hill, David A....
HPCA
2011
IEEE
13 years 2 months ago
Architectural framework for supporting operating system survivability
The ever increasing size and complexity of Operating System (OS) kernel code bring an inevitable increase in the number of security vulnerabilities that can be exploited by attack...
Xiaowei Jiang, Yan Solihin
HPCA
2011
IEEE
13 years 2 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
HPCA
2011
IEEE
13 years 2 months ago
Checked Load: Architectural support for JavaScript type-checking on mobile processors
Dynamic languages such as Javascript are the de-facto standard for web applications. However, generating efficient code for dynamically-typed languages is a challenge, because it...
Owen Anderson, Emily Fortuna, Luis Ceze, Susan Egg...
HPCA
2011
IEEE
13 years 2 months ago
CloudCache: Expanding and shrinking private caches
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilizatio...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
HPCA
2011
IEEE
13 years 2 months ago
Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing
Flash memory based solid state drives (SSDs) have shown a great potential to change storage infrastructure fundamentally through their high performance and low power. Most recent ...
Feng Chen, Rubao Lee, Xiaodong Zhang