Architectural Synthesis of Timed Asynchronous Systems

ions", in IEEE Transactions on CAD of VLSI, 25(3):403-412, March, 2006. , E. Mercer, C. Myers, "Modular Verification of Timed Systems Using Automatic Abstraction" in IEEE Transactions on CAD of VLSI, 22(9):1138-1153, September, 2003. E. Mercer, C. Myers, T. Yoneda, H. Zheng, "Modular Synthesis of Timed Circuits using Partial Order Reduction on LPN", in The Workshop on Theory and Practice of Timed Systems, April, 2002. , E. Mercer, C. Myers, "Automatic Abstraction for Hierarchical Verification of Timed Systems", in

• Type: Conference
• Year: 1999
• Where: ICCD
• Authors: Brandon M. Bachman, Hao Zheng, Chris J. Myers
• Keywords: Automatic Abstraction, Hardware, ICCD 1999, IEEE Transactions, Timed Systems