Verification Environment for a SCMP Architecture

The computer architecture of Single-chip multiprocessor (SCMP) is one of important research topics in developing the next-generation of computer hardware. A verification environment in the SCMP architecture, base of RISC microprocessor, acts as a functional verification simulator that elaborates its functions. This paper reports a simulation of the operational behavior in terms of function units. The simulation was in the mode of cycle-by-cycle when programs execute. The results of the SCMP simulation show that the simulation and its implementation can be used to effectively study the feasibility and applicability of the SCMP architecture.

• Type: Conference
• Year: 2006
• Where: IMSCCS
• Authors: Wenbin Yao, Nianmin Yao, Shaobin Cai, Jun Ni
• Keywords: Functional Verification Simulator, IMSCCS 2006, SCMP Architecture, Simulation