Architectures for function evaluation on FPGAs

This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for implementation on Field Programmable Gate Arrays (FPGAs). The method is exemplified with two common functions, sine and power-of-2. To test the performance of each design, we compare the proposed architecture to an established table-based method for several different input word-lengths and output precision requirements. FPGA-based results are presented, illustrating both the technology-independent and the technology-specific attributes of the tradeoff of area and speed between the proposed techniques.

• Type: Conference
• Year: 2003
• Where: ISCAS
• Authors: Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
• Keywords: ISCAS 2003, Multi-cycle Area-efficient Evaluation, Output Precision Requirements, Programmable Gate Arrays