Automatic generation of polynomial-based hardware architectures for function evaluation

Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture generator that inputs the specification of a function and outputs a synthesizable description of an architecture evaluating this function with guaranteed accuracy. It improves upon the literature in two aspects. Firstly, it uses better polynomials, thanks to recent advances related to constrained-coefficient polynomial approximation. Secondly, it refines the error analysis of polynomial evaluation to reduce the size of the multipliers used. An open-source implementation is provided in the FloPoCo project, including architecture exploration heuristics designed to use efficiently the embedded memories and multipliers of high-end FPGAs. High-performance pipelined architectures for precisions up to 64 bits can be obtained in seconds. Keywords-elementary function; hardware evaluator; polynomial approximation; FPGA;

• Type: Conference
• Year: 2010
• Where: ASAP
• Authors: Florent de Dinechin, Mioara Joldes, Bogdan Pasca
• Keywords: Architectures, ASAP 2010, Constrained-coefficient Polynomial Approximation, Hardware, Polynomial Approximation